1. Field of Invention
Embodiments of the present invention relate to a semiconductor memory device and a method of manufacturing the same and, more particularly, to a semiconductor memory device including a control gate and a method of manufacturing the same.
2. Description of Related Art
In order to achieve a higher integration degree of a NAND flash memory device, a gap between word lines becomes narrower. The narrower gap between the word lines may cause interference therebetween and deteriorate operating characteristics, which will be described below in detail.
FIG. 1 is a cross-sectional view of a conventional semiconductor memory device to illustrate an interference phenomenon.
Referring to FIG. 1, a P-well is formed in a semiconductor substrate. Cells of a NAND flash memory, which include source/drain S/D and cell gates (or word lines), are formed in the P-well. Each of the cell gates (or word lines) has a tunnel insulating layer Tox, a floating gate FG, a dielectric layer IPD and a control gate CG that are sequentially stacked. With increasing integration degree, the distances between the word lines are reduced.
During a program operation, a program voltage Vpgm is applied to a selected word line (i.e., a control gate of a cell gate) among the word lines, while a program pass voltage Vpass is applied to unselected word lines. Here, as distances between the word lines are reduced, interference may occur in unselected floating gates FG2 that are next to the selected word line during the program operation.
More specifically, since an insulating layer (not shown) is formed between a control gate CG1 of the selected word line and the floating gates FG2 of the unselected word lines next to the selected word line, parasitic capacitors Cp1 and Cp1 are formed by the control gate CG1, the dielectric layer IPD and the floating gates FG2. At this time, when the program voltage Vpgm is applied to the control gate CG1 of the selected word line, a high electric field may be applied to the floating gate FG2 of the neighboring word line because of capacitive coupling caused by the parasitic capacitor Cp1, whereby interference may occur. More specifically, the high electric field may cause electrons trapped in the floating gate FG2 to pass through the tunnel insulating layer Tox and be emitted to the substrate (particularly, P-well). Therefore, a threshold voltage of a memory cell that includes the floating gate FG2 may be reduced.
When a threshold voltage of a memory cell that has been programmed is reduced due to interference, data stored in the memory cell may be changed.